Summary

I have provided verification, design, support and management services for ASIC/FPGA digital designs and EDA & enterprise software since 1994. For six years prior, I managed a highly rated support team for an electronic design automation startup.

I create complex verification code and strategies, create and deliver training classes, write specifications and focused user documentation, automate regressions, manage releases, establish usable flow methodologies, manage or design as needed, and work within a schedule. I like to be part of the team.

Qualifications

§ A history of providing excellent language and tool support for complex software

§ Successful verifications of ASICs and FPGAs for ATM switching, packet analysis, and Firewire

§ Proficient with Verilog, VHDL, assertion-based checking, behavioral modeling, simulation and synthesis tools, bash, Perl, training development and documentation. Familiar with C, Vera, Tcl, PCI Express, USB, AMBA, PCI, memory controllers, formal verification.

§ Experience from concept through verification in ASIC and software design environments

Employment History

1994-2003 Contract Engineer

§ Test, coding, documentation at Jasper Design Automation – Verified, debugged, modified Verilog-based Formal Verification IP. Created databooks and tutorial for USB, PCI Express, and AMBA. [2003-2004, 8 months]

§ Test and documentation at Steelwedge - Extensively validated user interface and functionality while creating user guides, on-line help and training for Demand Forecasting software. [2002, 6 months]

§ Support and Release at Talus Solutions – (employee) Managed support to clients and consultants, developed and delivered training, specified and tested sales demos, edited documentation, and managed releases for enterprise level, J2EE-based pricing software. Implemented processes for successful customer and document management. Recruited staff. Member of merger integration team, the Interactive Voice Response System team, and Vantive merger team after Manugistics buyout. [2000-2002, 20 months]

§ Design Process Modification at NEC - Developed a structured VHDL-based design methodology to encourage high level design techniques. Re-coded dozens of example circuits reducing code length by factor of 5-10. Analyzed and critiqued existing design flow. Recommended significant new approaches. Presented training workshops at Shikoku and Ibaragi sites. [1997-2000, 2003, 7 months]

§ ASIC verification at Zayante - Developed testbenches for IEEE-1394A link and phy designs at block and chip levels. Contributed to model development for B version in Verilog and VHDL. This work was later productized by Apple as FireWire 800. [1998-2000, 15 months]

§ FPGA design and verification at Boeing’s Argo Systems - Designed Xilinx FPGA for reconfigurable PCI card for telecom Protocol Analyzer, monitoring incoming ATM streams and compiling data to memory. Developed automated test generation and assertion based results checking for the 4 FPGA chipset. Created design documentation. [1998-1999, 9 months]

§ Verification at ATM Systems - Worked with the ATM switching system development team under the guidance of Dr. Larry Roberts. Provided testbench development, language and tool support, and model creation for 3 of 5 ASICs. The test bench included directed and automated input, built-in assertion based output checking, and complex analysis routines for analyzing and graphing cell distribution, arbitration fairness, policing policies and ABR algorithm effectiveness. Provided tool and VHDL language expertise to the team. Implemented configuration management system for the design project team using RCS and C-shell scripting. Managed aspects of Phase 2 iteration of chip set. [1996-1998, 25 months]

§ Training - Training classes developed for and presented to UC Berkeley Extension, Cirrus Logic, Intel, and Lucent,: Topics included “Intro to VHDL Language”, "HDL for Synthesis Users", and “VHDL Testbenches”. [1995-1998, 75 training days]

§ IP Development - Model development of 4 MB Video Ram with accurate timing and verification IP. Built bus-functional, procedure based VHDL testbench for testing. Created Model Databook. Sold to LSI Logic, Megatek. [1995, 3 months]

§ Documentation at Altera - Created Synthesis Users Guide for MaxPlus2. [1995, 3 months]

§ Test and Debug at Zycad - Assembled automated testing and analysis suite for the VHDL Instruction Processor. Ported RASSP VHDL demonstration project to run on the supported subset. [1994, 6 months]

1987-1994 Engineer / Manager / Director / VP, Vantage Analysis Systems

Vantage developed and marketed the first commercially available VHDL simulator system, and grew from 0 to $14M in revenue with 1500 seats in 5 years. As the first tech support engineer, I was able to slowly assemble an outstanding customer support team, recognized in surveys as providing the industry leading expertise for early adopter VHDL clients.

§ Delivered world class tool & language support for clients, on-site and remotely

§ Built team of a dozen top notch design support engineers, plus support staff

§ Designed training classes presented to over 1000 engineers

§ Set and maintained high standards for training and product quality

§ Managed implementation of 5 volume Vantage SpeedWave documentation set

§ Specified and managed systems for order entry, billing, bug tracking, commissions, production, and shipping

§ Contributed significantly as team member to product features and functionality

§ Managed $1.5M operations budget

§ Vantage Employee of the Year 1991

Vantage was acquired by Viewlogic Systems Inc., December 1992.

EDUCATION

B.S. Physics, University of Delaware

Master’s Program, Electrical Engineering, University of Delaware, concentration in semiconductor materials, IC fabrication, optical switching, solar cell research

More…

Formerly

Radar Technician, Delaware Air National Guard

Trombonist, Treasurer, Technician: The Whale Band

Currently

Father, traveler, Frisbee tosser, dog hiker, home re-modeler